Title :
A new laser-processed polysilicon TFT architecture
Author :
Fulks, R.T. ; Ho, J. ; Boyce, J.B.
Author_Institution :
Electron. Mater. Lab., Xerox Palo Alto Res. Center, CA, USA
Abstract :
A new top gate polysilicon thin-film transistor (TFT) architecture is introduced which requires only a single laser process step to simultaneously crystallize the channel and activate the source-drain. The dummy-gate TFT (DGTFT) uses a light blocking layer patterned with the gate mask combined with two backside expose steps to allow a self-aligned device structure. N-channel TFTs fabricated using the new process have field effect mobilities greater than 100 cm/sup 2//Vs. By controlling the backside exposures it is also possible to form offset or graded doping structures to reduce field enhanced leakage currents.
Keywords :
carrier mobility; elemental semiconductors; laser beam annealing; recrystallisation annealing; silicon; thin film transistors; N-channel TFTs; Si-SiO/sub 2/; backside expose steps; channel crystallization; dummy-gate TFT; field effect mobilities; field enhanced leakage currents; gate mask patterning; graded doping structures; light blocking layer; offset structures; polysilicon TFT architecture; self-aligned device structure; single laser processing step; source-drain activation; top gate polysilicon thin-film transistor; transfer characteristics; Active matrix liquid crystal displays; Annealing; Crystallization; Doping; Glass; Implants; Plasma temperature; Resists; Substrates; Thin film transistors;
Journal_Title :
Electron Device Letters, IEEE
