Title :
Gate-Level Information-Flow Tracking for Secure Architectures
Author :
Tiwari, Mohit ; Li, Xun ; Wassel, Hassan M G ; Mazloom, Bita ; Mysore, Shashidhar ; Chong, Frederic T. ; Sherwood, Timothy
Author_Institution :
Univ. of California, Santa Barbara, CA, USA
Abstract :
This article describes a new method for constructing and analyzing architectures that can track all information flows within a processor, including explicit, implicit, and timing flows. The key to this approach is a novel gate-level information-flow-tracking method that provides a way to create complex logical structures with well-defined information-flow properties.
Keywords :
logic design; logic gates; microprocessor chips; private key cryptography; architecture analysis; architecture construction; complex logical structures; explicit timing flows; gate level information flow tracking; implicit timing flows; information flow properties; processor; secure architectures; Aerospace control; Aircraft manufacture; Control systems; Costs; Information analysis; Logic; Microprocessors; Military aircraft; Protection; Timing; covert channels; high-assurance systems; information-flow tracking; noninterference; timing channels;
Journal_Title :
Micro, IEEE
