Temperature-Oriented Mobility Measurement and Simulation to Assess Surface Roughness in Ultrathin-Gate-Oxide ( $\sim$ 1 nm) nMOSFETs and Its TEM Evidence

On a 1.27-nm gate-oxide nMOSFET, we make a comprehensive study of SiO₂/Si interface roughness by combining temperature-dependent electron mobility measurement, sophisticated mobility simulation, and high-resolution transmission electron microscopy (TEM) measurement. Mobility measurement and simulation adequately extract the correlation length λ and roughness rms height Δ of the sample, taking into account the Coulomb-drag-limited mobilities in the literature. The TEM measurement yields the apparent correlation length λm and roughness rms height Δm. It is found that the following hold: 1) λ ≈ λm for both the Gaussian and exponential models, validating the temperature-oriented extraction process; 2) the extracted Δ (~1.3 Å for the Gaussian model and 1.0 Å for the exponential one) is close to that (~1.2 Å) of Δm, all far less than the conventional values (~3 Å) in thick-gate-oxide case; and 3) the TEM 2-D projection correction coefficient Δm/Δ is approximately 1.0, which cannot be elucidated with the current thick-gate-oxide-based knowledge.