Title :
A 1.0-GHz single-issue 64-bit powerPC integer processor
Author :
Silberman, Joel ; Aoki, Naoaki ; Boerstler, David ; Burns, Jeffrey L. ; Dhong, Sang ; Essbaum, Axel ; Ghoshal, Uttam ; Heidel, David ; Hofstee, Peter ; Lee, Kyung Tek ; Meltzer, David ; Ngo, Hung ; Nowka, Kevin ; Posluszny, Stephen ; Takahashi, Osamu ; Vo
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
fDate :
11/1/1998 12:00:00 AM
Abstract :
The organization and circuit design of a 1.0 GHz integer processor built in 0.25 μm CMOS technology are presented, a microarchitecture emphasizing parallel computation with a single late select per cycle, structured control logic implemented by read-only-memories and programmable logic arrays, and a delayed reset dynamic circuit style enabling complex functions to be implemented in a few levels of logic are among the key design choices described. A means for at-speed scan testing of this high-frequency processor by a low-speed tester is also presented
Keywords :
CMOS digital integrated circuits; computer testing; integrated circuit design; integrated circuit testing; logic design; microprocessor chips; parallel architectures; 0.25 micron; 1 GHz; CMOS technology; at-speed scan testing; delayed reset dynamic circuit style; high-frequency processor; low-speed tester; microarchitecture; parallel computation; powerPC integer processor; programmable logic arrays; read-only-memories; single late select per cycle; single-issue integer processor; structured control logic; CMOS logic circuits; CMOS process; CMOS technology; Circuit synthesis; Circuit testing; Concurrent computing; Logic design; Microarchitecture; Programmable control; Programmable logic arrays;
Journal_Title :
Solid-State Circuits, IEEE Journal of
