Clocking design and analysis for a 600-MHz Alpha microprocessor

Author

Bailey, Daniel W. ; Benschneider, Bradley J.

Author_Institution

Compaq Comput. Corp., Shrewsbury, MA, USA

Volume

33

Issue

11

fYear

1998

fDate

11/1/1998 12:00:00 AM

Firstpage

1627

Lastpage

1633

Abstract

Design, analysis, and verification of the clock hierarchy on a 600 MHz Alpha microprocessor is presented. The clock hierarchy includes a gridded global clock, gridded major clocks, and many local clocks and local conditional clocks, which together improve performance and power at the cost of verification complexity. Performance is increased with a windowpane arrangement of global clock drivers for lowering skew and employing local clocks for time borrowing. Power is reduced by using major clocks and local conditional clocks. Complexity is managed by partitioning the analysis depending on the type of clock. Design and characterization of global and major clocks use both an AWEsim-based computer-aided design (CAD) tool and SPICE. Design verification of local clocks relies on SPICE along with a timing-based methodology CAD tool that includes data-dependent coupling, data-dependent gate loads, and resistance effects

Keywords

SPICE; circuit CAD; circuit analysis computing; delays; formal verification; microprocessor chips; timing; 600 MHz; AWEsim-based CAD tool; Alpha microprocessor; SPICE; clock hierarchy; clocking design; computer-aided design tool; data-dependent coupling; data-dependent gate loads; design verification; gridded global clock; gridded major clocks; local clocks; local conditional clocks; resistance effects; skew reduction; timing-based methodology; verification; windowpane arrangement; Clocks; Costs; Delay estimation; Design automation; Electromagnetic coupling; Hardware; Latches; Microprocessors; SPICE; Timing;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.726547

Filename

726547