DocumentCode :
1440018
Title :
A 1.2-W, 2.16-GOPS/720-MFLOPS embedded superscalar microprocessor for multimedia applications
Author :
Kubosawa, Hajime ; Takahashi, Hiromasa ; Ando, Satoshi ; Asada, Yoshimi ; Asato, Akira ; Suga, Atsuhiro ; Kimura, Michihide ; Higaki, Naoshi ; Miyake, Hideo ; Sato, Tomio ; Anbutsu, Hideaki ; Tsuda, Toshitaka ; Yoshimura, Tetsuo ; Amano, Isao ; Kai, Mutsu
Author_Institution :
Fujitsu Labs. Ltd., Kawasaki, Japan
Volume :
33
Issue :
11
fYear :
1998
fDate :
11/1/1998 12:00:00 AM
Firstpage :
1640
Lastpage :
1648
Abstract :
We have designed a microprocessor that is based on a single instruction multiple data stream (SIMD) architecture. It features a two-way superscalar architecture for multimedia embedded systems that need to support especially MPEG2 video decoding/encoding and 3DCG image processing. This microprocessor meets all requirements of embedded systems, including (a) MPEG2 (MP@ML) decoding and graphic processing capabilities for three-dimensional images, (b) programming flexibility, and (c) low power consumption and low manufacturing cost. High performance was achieved by enhanced parallel processing capabilities while adopting a SIMD architecture and a two-way superscalar architecture. Programming flexibility was increased by providing 170 dedicated multimedia instructions. Low power consumption was achieved by utilizing advanced process technology and power-saving circuits. The processor supports a general-purpose RISC instruction set. This feature is important, as the processor will have to work as a controller of various target systems. The processor has been fabricated by 0.21-μm CMOS four-metal technology on a 9.84×10.12 mm die. It performs 2.16 GOPS/720 MFLOPS at an operating frequency of 180 MHz, with a power consumption of 1.2 W and a power supply of 1.8 V
Keywords :
CMOS digital integrated circuits; decoding; image processing equipment; microprocessor chips; multimedia computing; parallel architectures; real-time systems; reduced instruction set computing; video coding; 0.21 micron; 1.2 W; 1.8 V; 180 MHz; 3D images; 3DCG image processing; 720 MFLOPS; CMOS four-metal technology; MPEG2 video decoding; MPEG2 video encoding; SIMD architecture; embedded superscalar microprocessor; enhanced parallel processing capabilities; general-purpose RISC instruction set; graphic processing capabilities; low manufacturing cost; low power consumption; multimedia applications; multimedia embedded systems; power-saving circuits; programming flexibility; single instruction multiple data stream; three-dimensional images; two-way superscalar architecture; CMOS technology; Decoding; Embedded system; Energy consumption; Graphics; Image coding; Image processing; Microprocessors; Multimedia systems; Streaming media;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/4.726550
Filename :
726550
Link To Document :
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