Title :
Low-power SRAM design using half-swing pulse-mode techniques
Author :
Mai, Kenneth W. ; Mori, Toshihiko ; Amrutur, Bharadwaj S. ; Ho, Ron ; Wilburn, Bennett ; Horowitz, Mark A. ; Fukushi, Isao ; Izawa, Tetsuo ; Mitarai, Shin
Author_Institution :
Center for Integrated Syst., Stanford Univ., CA, USA
fDate :
11/1/1998 12:00:00 AM
Abstract :
This paper describes a half-swing pulse-mode gate family that uses reduced input signal swing without sacrificing performance. These gates are well suited for decreasing the power in SRAM decoders and write circuits by reducing the signal swing on high-capacitance predecode lines, write bus lines, and bit lines. Charge recycling between positive and negative half-swing pulses further reduces the power dissipation. These techniques are demonstrated in a 2-K×16-b SRAM fabricated in a 0.25-μm dual-Vt CMOS technology that dissipates 0.9 mW operating at 1 V, 100 MHz, and room temperature. On-chip voltage samplers were used to probe internal nodes
Keywords :
CMOS memory circuits; SRAM chips; decoding; integrated circuit design; memory architecture; timing; 0.25 micron; 0.9 mW; 1 V; 100 MHz; 32 Kbit; CMOS technology; SRAM decoders; bit lines; charge recycling; half-swing pulse-mode techniques; high-capacitance predecode lines; low-power SRAM design; power dissipation reduction; signal swing reduction; static RAM; write bus lines; write circuits; CMOS technology; Capacitance; Circuits; Decoding; Leakage current; Power dissipation; Pulse amplifiers; Random access memory; Switches; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
