Title :
A 5-MHz, 3.6-mW, 1.4-V SRAM with nonboosted, vertical bipolar bit-line contact memory cell
Author :
Sato, Hirotoshi ; Nagaoka, Hideaki ; Honda, Hiroaki ; Maki, Yukio ; Wada, Tomohisa ; Arita, Yutaka ; Tsutsumi, Kazuhito ; Taniguchi, Makoto ; Yamada, Michihiro
Author_Institution :
NVM Dept., Mitsubishi Electr. Corp., Hyogo, Japan
fDate :
11/1/1998 12:00:00 AM
Abstract :
This paper describes a 256-Kbit SRAM fabricated using a novel bipolar bit-line contact memory cell having a large static noise margin. Vertical PNP transistors are introduced at the bit-line contact area, which realizes lower operational voltage and a memory-cell area equivalent to a 4-NMOS-type cell. The minimum operating voltage is 1.4 V without using a boosting technique, and the access time is 60 ns at a V cc of 1.8 V and room temperature. The power dissipation is 3.6 mW at a Vcc of 1.4 V. The operating Vcc range is 1.4-4.0 V
Keywords :
BiCMOS memory circuits; SRAM chips; integrated circuit noise; 1.4 to 4 V; 256 Kbit; 60 ns; SRAM; nonboosted bit-line memory cell; static RAM; static noise margin; vertical PNP transistors; vertical bipolar bit-line contact memory cell; Bipolar integrated circuits; Bipolar transistors; Boosting; Driver circuits; MOSFETs; Power dissipation; Random access memory; Semiconductor device noise; Temperature; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
