Title :
A 64-Mbit, 640-MByte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-MByte memory system
Author :
Kim, C.H. ; Lee, J.H. ; Lee, J.B. ; Kim, B.S. ; Park, C.S. ; Lee, S.B. ; Lee, S.Y. ; Park, C.W. ; Roh, J.G. ; Nam, H.S. ; Kim, D.G. ; Lee, D.Y. ; Jung, T.S. ; Yoon, H. ; Cho, S.I.
Author_Institution :
Samsung Electron. Co. Ltd., Kyungki-Do, South Korea
fDate :
11/1/1998 12:00:00 AM
Abstract :
A 64-Mbit bidirectional data strobed, double-data-rate SDRAM achieves a peak bandwidth of 2.56 GByte/s on a 64-bit-channel, 256-MByte memory system at Vcc=3.3 V and T=25°C. The circuit features are: (1) a bidirectional data strobing scheme to eliminate the clock-related skews of I/O data in a multimodule system, (2) a low-power delay-locked loop having a wide range of locking frequency (40-160 MHz) with fast access time and minimal variations, and (3) a twisted data bussing architecture with minimized loading difference between I/O data paths and small chip-size overhead associated with the 2-bit prefetch operation
Keywords :
DRAM chips; delay circuits; memory architecture; 25 degC; 256 MByte; 3.3 V; 40 mW; 40 to 160 MHz; 64 Mbit; 640 MByte/s; DLL; access time; bidirectional data strobed device; chip-size overhead; double-data-rate SDRAM; locking frequency; minimized loading difference; prefetch operation; twisted data bussing architecture; Bandwidth; Circuits; Clocks; Delay effects; Frequency; Graphics; Performance analysis; Prefetching; SDRAM; System performance;
Journal_Title :
Solid-State Circuits, IEEE Journal of
