Title :
Processor-based built-in self-test for embedded DRAM
Author :
Dreibelbis, Jeffrey ; Barth, John ; Kalter, Howard ; Kho, Rex
Author_Institution :
Microelectron. Div., IBM Corp., Essex Junction, VT, USA
fDate :
11/1/1998 12:00:00 AM
Abstract :
A built-in self-test engine and test methodology have been developed for testing a family of high-bandwidth, high-density DRAM macros. The DRAM macros range in size from 256×16×128 to 2 K×16×256 (Word×Bit×Data) and are targeted for embedded applications in application-specific integrated circuit designs. The processor-based test engine, with two separate instruction storage memories, combines with flexible address, data, and clock generators to provide DRAM high-performance ac testing using a minimum of dedicated test pins. Test results are compressed through on-macro, two-dimensional, redundancy allocation logic to provide direct programming information for the fuser via a serial scan port. The design is intended for reuse on future DRAM-generation subarrays and can be adapted to any number of address or data-pin configurations
Keywords :
application specific integrated circuits; built-in self test; integrated circuit testing; memory architecture; random-access storage; redundancy; DRAM-generation subarrays; application-specific integrated circuit designs; built-in self-test engine; clock generators; data-pin configurations; dedicated test pins; direct programming information; embedded DRAM; high-density DRAM macros; instruction storage memories; processor-based built-in self-test; redundancy allocation logic; serial scan port; test methodology; AC generators; Application specific integrated circuits; Automatic testing; Built-in self-test; Circuit testing; Clocks; Engines; Logic programming; Logic testing; Random access memory;
Journal_Title :
Solid-State Circuits, IEEE Journal of
