Title :
A 1.2-W single-chip MPEG2 MP@ML video encoder LSI including wide search range (H±288, V:±96) motion estimation and 81-MOPS controller
Author :
Ogura, Eiji ; Takashima, Masatoshi ; Hiranaka, Daisuke ; Ishikawa, Toshiro ; Yanagita, Yukio ; Suzuki, Shuji ; Fukuda, Tokuya ; Ishii, Toshiyuki
Author_Institution :
Media Processing Labs., Sony Corp., Tokyo, Japan
fDate :
11/1/1998 12:00:00 AM
Abstract :
An MPEG2 MP@ML video encoder large-scale integrated circuit (LSI) has been developed including an 81 MOPS controller and motion estimator. By using two adaptive algorithms, a wide motion-estimation search area (±288 pixels horizontal and ±96 pixels vertical) was achieved with computation complexity of only 0.5% (20 GOPS) of full search block-matching algorithm. By using this expanded motion-estimation search area, there is a significant improvement in picture quality for coding fast motion sequences. The power consumption was reduced by using an efficient pipeline architecture and optimizing the circuitry, especially in the motion-estimation block and the data transfers for the external SDRAM. The 13.7×12.4 mm2, 4.5-M transistor device using 0.4-μm CMOS technology dissipates 1.2 W at 3.3 V
Keywords :
CMOS digital integrated circuits; computational complexity; image matching; image sequences; large scale integration; motion estimation; pipeline processing; video coding; 0.4 micron; 1.2 W; 3.3 V; CMOS technology; MPEG2 MP@ML video; adaptive algorithms; computation complexity; data transfers; full search block-matching algorithm; motion estimation; motion sequences; picture quality; pipeline architecture; power consumption; search range; video encoder LSI; Adaptive algorithm; CMOS technology; Circuits; Computer architecture; Energy consumption; Large scale integration; Motion control; Motion estimation; Pipelines; SDRAM;
Journal_Title :
Solid-State Circuits, IEEE Journal of
