Check bit prediction scheme using Dong´s code for concurrent error detection in VLSI processors

The authors describe the application of Dong´s Code to the implementation of a checkbit prediction scheme for concurrent error detection (CED) in VLSI processors. Checkbit prediction is the only method which will permit the detection of both data transfer and data processing errors. Dong´s Code has the advantage that its error detection capability is a function of the number of checkbits used, independent of the number of databits being processed; that is the error detection capability of code can be made to be application specific. The applicability of the scheme for implementing a `CED´ test strategy in VLSI circuits is demonstrated by integrating this test method into a 32 bit RISC processor. The impact of the test scheme on the design is subsequently analysed in terms of area overheads and effect on performance. A comparison is made with two self-testing ALUs, one using Berger Code and the other Bose-Lin Code; Dong´s Code shows a reduction in the gate count required for checkbit prediction hardware for the ALU of 27 and 11%, respectively. When Dong´s Code was used for CED in the 32 bit RISC Processor, the area overhead incurred amounted to 55.5%, which is much less than duplication