Demonstration of Split-Gate Type Trigate Flash Memory With Highly Suppressed Over-Erase

Author

Kamei, Takahiro ; Liu, Yongxun ; Matsukawa, Takashi ; Endo, Kazuhiko ; O´uchi, Shinichi ; Tsukada, Junichi ; Yamauchi, Hiromi ; Ishikawa, Yuki ; Hayashida, Tetsuro ; Sakamoto, Kunihiro ; Ogura, Atsushi ; Masahara, Meishoku

Author_Institution

Sch. of Sci. & Technol., Meiji Univ., Kawasaki, Japan

Volume

33

Issue

3

fYear

2012

fDate

3/1/2012 12:00:00 AM

Firstpage

345

Lastpage

347

Abstract

The functional split-gate type trigate flash memory cell transistors have successfully been fabricated for the first time, and their threshold voltage (V_t) variations before and after NOR-mode program/erase cycle have systematically been compared with the stack-gate ones. It was experimentally found that split-gate type cell transistors with the same control gate length (L_CG) of 176 nm show much smaller Vt distribution after erase compared to those of stack-gate ones. Moreover, the measured source-drain breakdown voltage (BV_DS) is higher than 3.1 V even the L_CG was down to 76 nm. This indicates that the developed split-gate type trigate flash memory is very effective for scaled NOR-type flash memory with highly suppressed over-erase.

Keywords

MOSFET; flash memories; semiconductor device breakdown; semiconductor device measurement; voltage measurement; NOR-mode program-erase cycle; control gate length; highly suppressed over-erase; scaled NOR-type flash memory; source-drain breakdown voltage measurement; split-gate type trigate flash memory cell transistor; threshold voltage variations; Ash; Channel hot electron injection; Fabrication; Logic gates; Split gate flash memory cells; Transistors; Wet etching; Flash memory; over-erase; split gate; trigate;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2011.2181322

Filename

6145732