• DocumentCode
    1441246
  • Title

    Single-event upset and snapback in silicon-on-insulator devices and integrated circuits

  • Author

    Dodd, P.E. ; Shaneyfelt, M.R. ; Walsh, D.S. ; Schwank, J.R. ; Hash, G.L. ; Loemker, R.A. ; Draper, B.L. ; Winokur, P.S.

  • Author_Institution
    Sandia Nat. Labs., Albuquerque, NM, USA
  • Volume
    47
  • Issue
    6
  • fYear
    2000
  • fDate
    12/1/2000 12:00:00 AM
  • Firstpage
    2165
  • Lastpage
    2174
  • Abstract
    The characteristics of ion-induced charge collection and single-event upset are studied in silicon-on-insulator (SOI) transistors and circuits with various body tie structures. Impact ionization effects, including single-event snapback, are shown to be very important. Focused ion microbeam experiments are used to find single-event snapback drain voltage thresholds in n-channel SOI transistors as a function of device width. Three-dimensional device simulations are used to determine single-event upset and snapback thresholds in SOI SRAMs, and to study design tradeoffs for various body-tie structures. A window of vulnerability to single-event snapback is shown to exist below the single-event upset threshold. The presence of single-event snapback in commercial SOI SRAMs is confirmed through broadbeam ion testing, and implications for hardness assurance testing of SOI integrated circuits are discussed
  • Keywords
    CMOS memory circuits; SRAM chips; circuit simulation; focused ion beam technology; integrated circuit design; integrated circuit modelling; integrated circuit testing; radiation hardening (electronics); silicon-on-insulator; SOI SRAMs; SOI integrated circuits; body tie structures; design tradeoffs; device width; drain voltage thresholds; focused ion microbeam experiments; hardness assurance testing; ion-induced charge collection; silicon-on-insulator devices; single-event upset; snapback; three-dimensional device simulations; Body regions; Circuit simulation; Circuit testing; Dielectric substrates; Impact ionization; Integrated circuit testing; Silicon on insulator technology; Single event transient; Single event upset; Threshold voltage;
  • fLanguage
    English
  • Journal_Title
    Nuclear Science, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9499
  • Type

    jour

  • DOI
    10.1109/23.903749
  • Filename
    903749