Method for minimising the switching activity of two-level logic circuits

A new approach for implementing two-level logic circuits, which exhibit minimal power dissipation, is introduced. Switching activity reduction of the logic network nodes is achieved by inserting additional input signals in specific gates. Based on the statistical properties (i.e. static and transition probabilities) of the primary inputs, a new concept for grouping the input variables with similar features is presented. An efficient synthesis algorithm for generating the set of all classes of the variables, and solving the minimum covering problem for each class is developed. A comparison of the results produced by the proposed method, and those from ESPRESSO, shows that substantial power reduction can be achieved