• DocumentCode
    1441501
  • Title

    Layout Technique for Single-Event Transient Mitigation via Pulse Quenching

  • Author

    Atkinson, Nicholas M. ; Witulski, Arthur F. ; Holman, W. Timothy ; Ahlbin, Jonathan R. ; Bhuva, Bharat L. ; Massengill, Lloyd W.

  • Author_Institution
    Vanderbilt Univ., Nashville, TN, USA
  • Volume
    58
  • Issue
    3
  • fYear
    2011
  • fDate
    6/1/2011 12:00:00 AM
  • Firstpage
    885
  • Lastpage
    890
  • Abstract
    A layout technique that exploits single-event transient pulse quenching to mitigate transients in combinational logic is presented. TCAD simulations show as much as 60% reduction in sensitive area and 70% reduction in pulse width for some logic cells.
  • Keywords
    circuit layout; combinational circuits; transients; TCAD simulation; combinational logic cell; layout technique; pulse quenching; single-event transient mitigation; Inverters; Layout; Logic gates; Semiconductor device modeling; Solid modeling; Transient analysis; Transistors; Charge sharing; pulse quenching; single event; single-event transient; soft error;
  • fLanguage
    English
  • Journal_Title
    Nuclear Science, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9499
  • Type

    jour

  • DOI
    10.1109/TNS.2010.2097278
  • Filename
    5706391
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1441501