Systolic implementation on Kalman filters

Two schemes for implementing systolic and pipelined processing on Kalman filters in real time are presented. In the first, a single two-dimensional systolic processor is used to perform a Kalman filtering process. In the second scheme, the utilization of the two-dimensional systolic processor is fully expanded and improves the speed of updating estimates, Kalman filter algorithms are implemented on two concurrent, identical systolic processors. In both schemes, the mathematical formulation of the Kalman filter algorithms is rearranged to be the type of the Faddeeva algorithm for generalizing matrix/vector manipulations. The corresponding data flow is easily mapped from algorithms into the computing structure which is of nearest neighbor type. The architecture of the processor cells is regular, simple, expandable, and suitable for VLSI implementation. The computing methodology and the two-dimensional systolic arrays are useful for Kalman filter applications as well as general matrix/vector algebraic computations