Title :
A digital CMOS design technique for SEU hardening
Author :
Baze, Mark P. ; Buchner, Steven P. ; McMorrow, Dale
Author_Institution :
Boeing Co., Seattle, WA, USA
fDate :
12/1/2000 12:00:00 AM
Abstract :
A new cell design technique is described which may be used to create SEU hardened circuits. The technique uses actively biased, isolated well transistors to prevent transients in combinational logic from reaching the output node
Keywords :
CMOS logic circuits; cellular arrays; combinational circuits; integrated circuit design; radiation hardening (electronics); transients; CMOS design technique; SEU hardening; actively biased isolated well transistors; cell design technique; combinational logic; digital CMOS; output node; transients; CMOS logic circuits; CMOS technology; Clocks; Error analysis; Impedance; Inverters; Logic design; Registers; Resistors; Single event upset;
Journal_Title :
Nuclear Science, IEEE Transactions on
