• DocumentCode
    1441750
  • Title

    A digital CMOS design technique for SEU hardening

  • Author

    Baze, Mark P. ; Buchner, Steven P. ; McMorrow, Dale

  • Author_Institution
    Boeing Co., Seattle, WA, USA
  • Volume
    47
  • Issue
    6
  • fYear
    2000
  • fDate
    12/1/2000 12:00:00 AM
  • Firstpage
    2603
  • Lastpage
    2608
  • Abstract
    A new cell design technique is described which may be used to create SEU hardened circuits. The technique uses actively biased, isolated well transistors to prevent transients in combinational logic from reaching the output node
  • Keywords
    CMOS logic circuits; cellular arrays; combinational circuits; integrated circuit design; radiation hardening (electronics); transients; CMOS design technique; SEU hardening; actively biased isolated well transistors; cell design technique; combinational logic; digital CMOS; output node; transients; CMOS logic circuits; CMOS technology; Clocks; Error analysis; Impedance; Inverters; Logic design; Registers; Resistors; Single event upset;
  • fLanguage
    English
  • Journal_Title
    Nuclear Science, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9499
  • Type

    jour

  • DOI
    10.1109/23.903815
  • Filename
    903815
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1441750