Accurate statistical process variation analysis for 0.25-μm CMOS with advanced TCAD methodology

Effects of statistical process variation on the 0.25-μm CMOS performance have been accurately characterized by using a new calibrated TCAD methodology. To conduct the variation analysis, a series of TCAD simulations was conducted on the basis of DoE (design of experiments) with optimum variable transformations, which resulted in RSF´s (response surface functions) for threshold voltage (V_th) and saturation drain current (I_ds). A new global calibration of the RSF model based on experimental data gives excellent accuracy within 0.02 V error in V_th and 3% error in I_ds. Using calibrated RSF, statistical process variation effects on the device characteristics have been quantitatively evaluated for each process recipe. It is found that variation of the gate-oxide formation process shows the most significant effect on the NMOS ΔI_ds in the production process. Furthermore we have designed an optimized 0.25-μm CMOS process and device on the basis of the RSF and also predicted the process variation effects on the device performance. It is shown that the V_th and I_ds variations of the 0.25-μm CMOS exhibit less than 10% I_ds variation in the production level process, which is similar to the value of 0.35-μm CMOS experimental data. Additional TCAD simulations for MOS model parameter generation of the 0.25-μm device was also conducted to allow circuit-designers to use predictive worst case circuit design parameters before experimental chip fabrication