Planning wafer allocation for CMOS process development. A nonparametric approach

Author

Rao, Suraj ; Vasanth, Karthik ; Mozumder, Purnendu K. ; Saxena, Sharad ; Davis, Joseph C. ; Burch, Richard

Author_Institution

Silicon Technol. Dev., Texas Instrum. Inc., Dallas, TX, USA

Volume

11

Issue

4

fYear

1998

fDate

11/1/1998 12:00:00 AM

Firstpage

583

Lastpage

590

Abstract

In this paper, we present techniques that can be used to answer the following two questions: (1) how many wafers need to be allocated per treatment to detect a given difference in a device performance metric and (2) how can one determine if a given treatment significantly improved a performance metric? The approach presented here does not make any assumptions regarding the shape of the distribution or the spatial dependency structure for the within-wafer performance measurements and remains applicable for a variety of performance metrics, such as mean, variance, and median. The analysis method can be used in decisions regarding the appropriateness of allocating half or quarter wafer splits to a treatment. Furthermore, the approach allows us to evaluate and compare within-wafer sampling strategies for comparing performance metrics from competing flows

Keywords

CMOS integrated circuits; integrated circuit measurement; manufacturing resources planning; nonparametric statistics; production testing; statistical analysis; CMOS process development; device performance metric; nonparametric approach; spatial dependency structure; wafer allocation; wafer splits; within-wafer performance measurements; within-wafer sampling strategies; CMOS process; CMOS technology; Fluid flow measurement; Metrology; Process planning; Sampling methods; Shape measurement; Standards development; Testing; Threshold voltage;

fLanguage

English

Journal_Title

Semiconductor Manufacturing, IEEE Transactions on

Publisher

ieee

ISSN

0894-6507

Type

jour

DOI

10.1109/66.728555

Filename

728555