• DocumentCode
    1443429
  • Title

    Layout Proximity Effects and Modeling Alternatives for IC Designs

  • Author

    Lin, Xi-Wei ; Moroz, Victor

  • Author_Institution
    Silicon Eng. Group, Synopsys, Mountain View, CA, USA
  • Volume
    27
  • Issue
    2
  • fYear
    2010
  • Firstpage
    18
  • Lastpage
    25
  • Abstract
    Layout-dependent variations significantly affect device modeling, model extraction, and design solutions. A novel approach is proposed in this article to seamlessly integrate physical models of lithography, strained Si, and ion implantation processes, with layout geometry for efficient model generation.
  • Keywords
    integrated circuit layout; integrated circuit modelling; ion implantation; proximity effect (lithography); IC designs; device modeling; ion implantation process; layout geometry; layout proximity effects; layout-dependent variations; lithography; model extraction; modeling alternatives; CMOS integrated circuits; CMOS technology; Compressive stress; Integrated circuit layout; Integrated circuit modeling; Lithography; Optical scattering; Proximity effect; Semiconductor device modeling; Silicon; CMOS; compact model; design and test; extraction; layout; lithography; mobility; proximity; stress; threshold voltage; variability;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/MDT.2010.48
  • Filename
    5432319
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1443429