DocumentCode
1443527
Title
A ´delayed layering´ three layer channel routing
Author
Chang, K.E. ; Feng, W.-S.
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Volume
137
Issue
4
fYear
1990
fDate
7/1/1990 12:00:00 AM
Firstpage
229
Lastpage
238
Abstract
A new three-layer channel router with ´delayed layering´ technique is presented. The delayed layering scheme in the routing can improve the capability of the router to reach comprehensive objectives. This new router not only minimises the tracks used, but also minimises the via usage and maximises the use of preferred routing layers. The delayed layering router consists of two steps: track assignment and layer assignment. The track assignment uses a topological sorting algorithm to determine the horizontal track number of every net. A layerless layout will result from the track assignment. The layer assignment heuristically determines which layers can be used for routing the wire segments in the layerless layout, such that the vias generated are as small as possible. The experiments showed that the solution quality with respect to via usage was better than the previous solutions and the number of tracks used in channel was satisfactory.
Keywords
VLSI; circuit layout CAD; VLSI layout; delayed layering; horizontal track number; layer assignment; three layer channel routing; topological sorting algorithm; track assignment; via usage; wire segments;
fLanguage
English
Journal_Title
Computers and Digital Techniques, IEE Proceedings E
Publisher
iet
ISSN
0143-7062
Type
jour
Filename
54325
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