Oscillation frequency in CML and ESCL ring oscillators

Author

Alioto, M. ; Palumbo, G.

Author_Institution

Catania Univ., Italy

Volume

48

Issue

2

fYear

2001

fDate

2/1/2001 12:00:00 AM

Firstpage

210

Lastpage

214

Abstract

In this paper a model to accurately evaluate even in a pencil-and-paper manner the oscillation frequency of a ring oscillator made up by a CML or ESCL differential gate is proposed. The model allows us to simply estimate the oscillation frequency changes due both to the bias current change and to process tolerances. The model was validated by Spice simulations on both 6- and 20-GHz technologies for the CML ring oscillator, and on 0.8-μm CMOS process for the ESCL ring oscillator. The estimated oscillation frequency agrees with the simulated one. Indeed, average errors lower than 10% were found

Keywords

CMOS logic circuits; SPICE; bipolar logic circuits; circuit simulation; current-mode logic; logic simulation; 0.8 micron; 20 GHz; 6 GHz; CML; CMOS process; ESCL; Spice simulations; average errors; bias current change; current mode logic; differential gate; oscillation frequency changes; process tolerances; ring oscillators; CMOS logic circuits; CMOS process; CMOS technology; Circuit simulation; Frequency estimation; Integrated circuit technology; Negative feedback; Propagation delay; Ring oscillators; Semiconductor device modeling;

fLanguage

English

Journal_Title

Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on

Publisher

ieee

ISSN

1057-7122

Type

jour

DOI

10.1109/81.904885

Filename

904885