Scalable PD/SOI CMOS with floating bodies

Author

Fossum, Jerry G. ; Pelella, Mario M. ; Krishnan, Srinath

Author_Institution

Dept. of Electr. & Comput. Eng., Florida Univ., Gainesville, FL, USA

Volume

19

Issue

11

fYear

1998

Firstpage

414

Lastpage

416

Abstract

An insightful analysis of the floating-body (FB) effect on off-state current (I/sub off/) in PD/SOI MOSFETs is done based on simulations calibrated to a published scaled SOI CMOS technology (Chau et al., 1997). In contrast to the conclusion drawn by Chau, the simulations reveal that proven, easily integrated processes for enhancing carrier recombination in the source/drain junction region, in conjunction with the normal elevated chip temperature of operation, can effectively suppress the FB-induced increase of I/sub off/, thus enabling exploitation of the unique benefits of scaled PD/SOI CMOS circuits.

Keywords

CMOS integrated circuits; MOSFET; SPICE; circuit simulation; semiconductor device models; silicon-on-insulator; SOI MOSFET; SOISPICE; carrier recombination enhancement; floating bodies; floating-body effect; integrated processes; off-state current; scalable partially depleted/SOI CMOS; scaled SOI CMOS technology; simulation; source/drain junction region; subthreshold I-V characteristics; Analytical models; CMOS logic circuits; CMOS process; CMOS technology; Circuit simulation; MOSFET circuits; Predictive models; Scalability; Temperature; Threshold voltage;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.728897

Filename

728897