Title :
Spacer Gate Lithography for Reduced Variability Due to Line Edge Roughness
Author :
Sun, Xin ; Liu, Tsu-Jae King
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Berkeley, CA, USA
fDate :
5/1/2010 12:00:00 AM
Abstract :
The effect of gate line edge roughness (LER) on bulk-Si MOSFET performance is studied using 3-D device simulations. The benefit of using a spacer (sidewall transfer) gate lithography process to mitigate the effect of LER is assessed, with consideration of source/drain placement and spacer width variation. The simulation results indicate that spacer gate lithography can dramatically reduce LER-induced variation in transistor performance and that variability can be well suppressed with gate-length scaling even if LER does not scale.
Keywords :
MOSFET; lithography; simulation; 3D device simulations; MOSFET; line edge roughness; reduced variability; spacer gate lithography; transistor; Line edge roughness (LER); scalability; spacer lithography; variability;
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
DOI :
10.1109/TSM.2010.2046050