A 20-GHz Bipolar Latched Comparator With Improved Sensitivity Implemented in InP HBT Technology

Author

Kraus, Shraga ; Kallfass, Ingmar ; Makon, Robert E. ; Driad, Rachid ; Moyal, Michael ; Ritter, Dan

Author_Institution

Dept. of Electr. Eng., Technion - Israel Inst. of Technol., Haifa, Israel

Volume

59

Issue

3

fYear

2011

fDate

3/1/2011 12:00:00 AM

Firstpage

707

Lastpage

715

Abstract

A method for improving the sensitivity (or speed) of a master-slave emitter-coupled logic comparator using emitter degeneration resistors is presented. The degeneration resistors in the latching pair reduce the transistor charging time, thus allowing more time for regeneration. Improved and standard comparators were implemented using the InP/GaInAs heterojunction bipolar transistor technology and were tested at a clock rate of 20 GHz. The improved comparator exhibited better sensitivity (by a factor of 1.7) compared to the standard design. A record low-sensitivity value of 10 mV was obtained.

Keywords

III-V semiconductors; comparators (circuits); emitter-coupled logic; flip-flops; gallium compounds; heterojunction bipolar transistors; indium compounds; InP-GaInAs; bipolar latched comparator; emitter degeneration resistors; frequency 20 GHz; master-slave emitter-coupled logic comparator; transistor charging time; voltage 10 mV; Capacitance; Clocks; Resistance; Resistors; Sensitivity; Switches; Transistors; Bipolar comparators; emitter coupled logic (ECL); heterojunction bipolar transistors (HBTs); latched comparators; master–slave comparators; sensitivity;

fLanguage

English

Journal_Title

Microwave Theory and Techniques, IEEE Transactions on

Publisher

ieee

ISSN

0018-9480

Type

jour

DOI

10.1109/TMTT.2011.2104974

Filename

5710035