Title :
Selective negative word line scheme for improving refresh
Author :
Lee, M.J. ; Park, K.W. ; Ahn, J.H.
Author_Institution :
R&D Div., Hynix Semicond. Inc., Icheon, South Korea
Abstract :
Proposed is a new selective negative word line scheme that yields almost 2.7% of the fail bit count (FBC) in a DRAM chip with a conventional negative word line scheme in the pause refresh state. It has a superior dynamic refresh characteristic, which is almost 0.3% of the FBC in a DRAM chip using the ground word line scheme. This scheme leads to a very low cell VTH (threshold voltage).
Keywords :
DRAM chips; DRAM chip; dynamic refresh characteristic; fail bit count; ground word line scheme; pause refresh state; selective negative word line scheme;
Journal_Title :
Electronics Letters
DOI :
10.1049/el.2010.3643
