ASIC implementation of fractionally spaced Rake receiver for high data rate UWB systems

An ASIC implementation scheme of a fractionally spaced Rake (FS-Rake) receiver is presented for high data rate UWB systems to save hardware resources and avoid routing congestion. In this scheme, one pre-combining module and two stages of shift register and multiplexer are employed for multipath selection. ASIC implementation results demonstrate that the proposed scheme can save 13.1% cell area compared with the conventional FS-Rake structure. More importantly, routed nets are reduced by 37.2%. Therefore, serious routing congestion that is an obstacle to design convergence is mitigated effectively in this proposed scheme.