Title :
Depletion-region width of p-n junction under high forward-bias conditions
Author :
Jain, L.C. ; Garud, G.N.
Author_Institution :
Visvesvaraya Regional College of Engineering, Department of Electrical Engineering, Nagpur, India
fDate :
5/1/1979 12:00:00 AM
Abstract :
A new technique is used for the accurate analysis of linearly graded and Gaussian-graded p-n junctions, which permits calculation of the depletion-region width under high forward-bias conditions. Such an analysis is very useful for applications in which one wishes to analyse a complete junction-device structure (such as a bipolar transistor). The results obtained represent a considerable improvement in space-charge modelling over previous approaches to approximate linear analysis. The computer algorithm is discussed as a solution process for implementing the scheme.
Keywords :
electronic engineering computing; p-n junctions; semiconductor device models; Gaussian graded; approximate linear analysis; computer algorithm; depletion region width under high forward bias conditions; linearly graded; p-n junctions; space charge modelling;
Journal_Title :
Electrical Engineers, Proceedings of the Institution of
DOI :
10.1049/piee.1979.0089
