Hybrid $C$ – $V$ and $I$ <

We report a hybrid technique for extraction of structure- and gate-bias-dependent parasitic source/drain (S/D) resistances (RS and RD) in amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs). In the proposed technique, C- V and I -V measurements are combined for modeling and extraction. As structural dependence, the active-layer thickness T_IGZO , the gate length L, and the overlap length L_ov between the S/D and the gate are considered in the equivalent circuit for parasitic resistances. We also separated the horizontal component RH considering the transfer resistance R_LT depending on the transfer length LT and the channel resistance R_CH, as well as the vertical components in the S/D R_VS and R_VD. We confirmed the proposed technique through a separate extraction of VGS -independent contact resistances (R_CS, R_CD) from the channel length- and VGS-dependent R_LT and R_CH.