Title :
Hybrid Floating Gate Cell for Sub-20-nm NAND Flash Memory Technology
Author :
Blomme, P. ; Cacciato, A. ; Wellekens, D. ; Breuil, L. ; Rosmeulen, M. ; Kar, G.S. ; Locorotondo, S. ; Vrancken, C. ; Richard, O. ; Debusschere, I. ; Van Houdt, J.
Author_Institution :
IMEC, Leuven, Belgium
fDate :
3/1/2012 12:00:00 AM
Abstract :
The hybrid floating gate (FG) concept, previously demonstrated in FG capacitors, has been proven in fully integrated stacked memory cells. Results not only confirm the high potential of the concept in terms of improved program performance, but also show excellent data retention and program/erase cycling endurance. Key for achieving this result has been the optimization of the sidewall and spacer processing. Hybrid FG cells are therefore a viable solution to extend the nand Flash memory roadmap below the 20-nm technology node.
Keywords :
MOSFET; capacitors; circuit optimisation; flash memories; FG capacitor; NAND flash memory technology; data retention; erase cycling endurance; fully integrated stacked memory cell; hybrid FG cell; hybrid floating gate cell; program performance; sidewall processing; size 20 nm; spacer processing; Annealing; Ash; Couplings; Flash memory; Logic gates; Metals; Programming; Cell integration; dual-layer floating gate (FG); nand flash memory scaling;
Journal_Title :
Electron Device Letters, IEEE
DOI :
10.1109/LED.2011.2181152
