A 1.8 GHz CMOS high-linear power-combining power amplifier using on-chip transmission line transformer

Author

Ming-Yi Chen ; Jeng-Rern Yang

Author_Institution

Dept. of Commun. Eng., Yuan Ze Univ., Jhongli, Taiwan

Volume

2

fYear

2014

fDate

26-28 April 2014

Firstpage

694

Lastpage

696

Abstract

A fully integrated power amplifier using 0.18 um CMOS process is presented. The proposed design utilizes an on-chip transmission line transformer as a power combiner and a matching network. With 3.5 V supply, the dc consumption is 179 mA. The simulated results show that the linear gain is 12 dB at 1.8 GHz, and 1-dB gain-compressed output power is 27 dBm, while the power added efficiency is 24%. The amplifier delivers an average output power of 21 dBm under an adjacent channel leakage ratio (ACLR) of -30 dBc for a 10-MHz bandwidth 16-QAM LTE uplink signal while error vector magnitude (EVM) is 2.3%. The layout size is 1.2 mm by 1.2 mm.

Keywords

CMOS analogue integrated circuits; Long Term Evolution; UHF power amplifiers; power combiners; quadrature amplitude modulation; transformers; transmission lines; 16-QAM LTE uplink signal; ACLR; CMOS high-linear power-combining power amplifier; adjacent channel leakage ratio; bandwidth 10 MHz; current 179 mA; efficiency 24 percent; error vector magnitude; frequency 1.8 GHz; gain 1 dB; gain 12 dB; matching network; on-chip transmission line transformer; size 0.18 mum; voltage 3.5 V; CMOS integrated circuits; Gain; Impedance matching; Power amplifiers; Power generation; Power transmission lines; System-on-chip; CMOS; power amplifier; power combining; transmission line transformer (TLT);

fLanguage

English

Publisher

ieee

Conference_Titel

Information Science, Electronics and Electrical Engineering (ISEEE), 2014 International Conference on

Conference_Location

Sapporo

Print_ISBN

978-1-4799-3196-5

Type

conf

DOI

10.1109/InfoSEEE.2014.6947754

Filename

6947754