DocumentCode
1445639
Title
Possibilities and limitations of IDDQ testing in submicron CMOS
Author
Figueras, Joan ; Ferre, Antoni
Author_Institution
Electronic Engineering Department, Polytechnic University of Catalonia, Barcelona 08028, Spain
Volume
21
Issue
4
fYear
1998
Firstpage
352
Lastpage
359
Abstract
IDDQ Testing is a well accepted testing approach based on the observation of the quiescent current consumption. Its growing industrial implementation is based on the possibility of detecting defects which escape other more traditional testing methods. However, its application costs are higher and its effectiveness in deep submicron technologies may decrease if the current trend of leakage increase is not stopped by creative innovation.
Keywords
conducting polymers; electrical contacts; environmental stress screening; flip-chip devices; integrated circuit packaging; 2 to 5 micron; attachment materials; electrical contact; flip-chip attachment; polymeric conductive pastes; thermoplastic pastes; thermoset pastes; Assembly; Conducting materials; Contacts; Costs; Packaging; Polymers; Stress; Testing; Vehicles; Viscosity; CMOS scaling trends; IDDQ test threshold; current testing; leakage power consumption; quiescent currents;
fLanguage
English
Journal_Title
Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on
Publisher
ieee
ISSN
1070-9894
Type
jour
DOI
10.1109/96.730419
Filename
730419
Link To Document