Accurately Handle Don´t-Care Conditions in High-Level Designs and Application for Reducing Initialized Registers

Don´t-care conditions are utilized by many synthesis tools because such conditions provide additional flexibility for logic optimization. However, most techniques only focus on the gate level because it is difficult to handle such conditions accurately at behavior and register transfer levels. This is problematic since the trend is to move toward high-level synthesis. In this paper, we propose innovative methods to handle such conditions accurately at high-level designs. In addition, we propose three novel algorithms based on our new methods to minimize the number of registers that need to be initialized, which can reduce the routing resources used by the reset signals and alleviate the routing problem. We applied our techniques to a five-stage pipelined processor and successfully reduced the number of control registers that need to be initialized by 53%, demonstrating the effectiveness of our approach.