Title :
Fully integrated standard cell digital PLL
Author :
Olsson, T. ; Nilsson, P.
Author_Institution :
Dept. of Appl. Electron., Lund Univ., Sweden
fDate :
2/15/2001 12:00:00 AM
Abstract :
A fully integrated digital phase-locked loop (PLL) used as a clock multiplying circuit is designed. The PLL is made from standard cells found in almost any commercial standard cell library and therefore portable between processes in netlist format. Using a 0.35 μm standard complementary metal-oxide-semiconductor CMOS process and a 3.0 V supply voltage, the PLL is designed for a locking range of 170 to 360 MHz and occupies an on-chip area of 0.06 mm2
Keywords :
CMOS digital integrated circuits; cellular arrays; clocks; digital phase locked loops; 0.35 micron; 170 to 360 MHz; 3.0 V; CMOS integrated circuit; clock multiplying circuit; digital phase locked loop; standard cell;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20010160
