DocumentCode :
1446430
Title :
A Co-Design Approach for SET Mitigation in Embedded Systems
Author :
Lindoso, Almudena ; Entrena, Luis ; Millán, Enrique San ; Cuenca-Asensi, Sergio ; Martínez-Álvarez, Antonio ; Restrepo-Calle, Felipe
Author_Institution :
Electronic Technology Department, University Carlos III of Madrid, Avda. Universidad, Madrid, Spain
Volume :
59
Issue :
4
fYear :
2012
Firstpage :
1034
Lastpage :
1039
Abstract :
We propose a new methodology for hardware/software co-design of embedded systems which is specifically aimed to mitigate SET effects. A hardening infrastructure is used to generate different versions of the design using several combinations of hardware and software hardening which are evaluated with respect to SET effects. The advantages of the proposed approach are demonstrated by means of a case study.
Keywords :
Benchmark testing; Circuit faults; Clocks; Error analysis; Hardware; Registers; Software; Fault tolerance; radiation effects; single event transient; soft error;
fLanguage :
English
Journal_Title :
Nuclear Science, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9499
Type :
jour
DOI :
10.1109/TNS.2011.2182524
Filename :
6151198
Link To Document :
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