Title :
8-Bit Asynchronous Wave-Pipelined RSFQ Arithmetic-Logic Unit
Author :
Filippov, T. ; Dorojevets, M. ; Sahu, A. ; Kirichenko, A. ; Ayala, C. ; Mukhanov, O.
Author_Institution :
HYPRES Inc., Elmsford, NY, USA
fDate :
6/1/2011 12:00:00 AM
Abstract :
We have designed and demonstrated an Arithmetic-Logic Unit (ALU) based on RSFQ technology as a required step toward building an 8-bit RSFQ processor datapath. The circuit was designed and fabricated with HYPRES´ standard 4.5 kA/cm2 process. The target clock frequency of the ALU is 20 GHz. In this paper, we present the design and functionality (low-speed) test results of the 8-bit ALU.
Keywords :
adders; superconducting logic circuits; HYPRES standard process; RSFQ processor datapath; adder; arithmetic-logic unit; asynchronous wave-pipeline; frequency 20 GHz; word length 8 bit; Adders; Clocks; Computer architecture; Layout; Microarchitecture; Microprocessors; Pipelines; ALU; Adder; RSFQ; SFQ; microprocessor; timing;
Journal_Title :
Applied Superconductivity, IEEE Transactions on
DOI :
10.1109/TASC.2010.2103918
