A 15-b, 5-Msample/s low-spurious CMOS ADC

Author

Kwak, Sung-Ung ; Song, Bang-Sup ; Bacrania, Kantilal

Author_Institution

Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA

Volume

32

Issue

12

fYear

1997

fDate

12/1/1997 12:00:00 AM

Firstpage

1866

Lastpage

1875

Abstract

A 5-5-5-6-b pipelined analog-to-digital converter (ADC) architecture alleviates the requirements for initial capacitor matching and residue amplifier settling accuracy. The two 5-b most significant bit (MSB) stages are digitally calibrated to implement a 15-b, 5-Msample/s low-spurious ADC using 1.4-μm CMOS. A skip-and-fill algorithm with nonlinear interpolation also opens up the possibility of calibrating ADC´s in the background synchronously with their normal operation. Interpolation results for the background calibration are compared with the foreground calibration results. The prototype ADC exhibits a differential nonlinearity (DNL) of +0.75/-0.6 least significant bit (LSB), an integral nonlinearity (INL) of +1.77/-1.58 LSB, and all spurious components are suppressed to below -93 dB when sampled at 5 MHz. The chip occupies 27 mm², and the analog part consumes 60 mW at 5 V. Memory and arithmetic units for calibration are supplied externally in testing

Keywords

CMOS integrated circuits; analogue-digital conversion; calibration; interpolation; pipeline processing; CMOS ADC; background calibration; differential nonlinearity; foreground calibration; initial capacitor matching; integral nonlinearity; interpolation results; most significant bit stages; nonlinear interpolation; pipelined analog-to-digital converter; residue amplifier settling accuracy; skip-and-fill algorithm; Analog-digital conversion; Calibration; Capacitors; Digital filters; Dynamic range; High power amplifiers; Interpolation; Linearity; Radio frequency; Sampling methods;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.643645

Filename

643645