Feature-Ranking Methodology to Diagnose Design-Silicon Timing Mismatch

For sub-65-nm design, many timing effects, if not explicitly and accurately modeled and simulated, can result in an unexpected timing mismatch between simulated and observed timing behavior on silicon chips. We describe a feature-ranking methodology to analyze and rank potential design-related issues, explaining how diverse features can be used to encode the potential design issues and how features can be interpreted properly.