Title :
High-resolution time-to-digital converter utilising fractional difference conversion scheme
Author :
Xing, N. ; Shin, Won-Yong ; Jeong, Deog-Kyoon ; Kim, Sungho
Author_Institution :
Electr. Eng., Seoul Nat. Univ., Seoul, South Korea
Abstract :
A high-resolution process, voltage and temperature (PVT)-insensitive time-to-digital converter (TDC) is presented, based on a Vernier delay-line, in which the propagation delays in the upper and lower buffer chains are stabilised by two different delay-locked-loops (DLLs). The limitation on its resolution, imposed by DLL jitter and input range of time intervals, is analysed. Simulation results show that the proposed TDC achieves a resolution as high as 22.7 ps while consuming only 2.7 mW.
Keywords :
convertors; delay lines; delay lock loops; jitter; DLL jitter; PVT-insensitive time-to-digital converter; Vernier delay-line; delay-locked-loop; fractional difference conversion; high-resolution process-voltage-and-temperature; high-resolution time-to-digital converter; lower buffer chain; power 2.7 mW; propagation delay; upper buffer chain;
Journal_Title :
Electronics Letters
DOI :
10.1049/el.2010.2698
