Phase-locked loop based Δ-Σ ADC

A phase-locked loop (PLL) based delta-sigma analogue-to-digital converter architecture providing second-order noise shaping is presented. By combining a low power passive integrator with a voltage-controlled oscillator-based integrator, the proposed architecture suppresses the oscillator nonlinearity with minimum hardware penalty. Simulation results indicate 14-bit performance by using only a 4-bit linear oscillator.