Title :
Design of multipliers for GF(2m)
Author :
Mao, Zhi-Hong ; Shou, Guofa ; Hu, Ya ; Guo, Zhiyou
Author_Institution :
Sch. of Inf. & Commun. Eng., Beijing Univ. of Posts & Telecommun., Beijing, China
Abstract :
A new design of multipliers for GF(2m) based on combination of bit-serial and bit-parallel schemes with low complexity is proposed. Using pipeline architecture, the scheme yields significantly lower latency compared to known bit-parallel multipliers for GF(2m).
Keywords :
Galois fields; logic design; multiplying circuits; pipeline processing; Galois fields; bit-parallel multiplier; bit-serial multiplier; low complexity; pipeline architecture;
Journal_Title :
Electronics Letters
DOI :
10.1049/el.2010.0246
