DocumentCode :
1447240
Title :
692-nW Advanced Encryption Standard (AES) on a 0.13- 
m CMOS
Author :
Good, T. ; Benaissa, M.
Author_Institution :
Dept. of Electr. & Electron. Eng., Univ. of Sheffield, Sheffield, UK
Volume :
18
Issue :
12
fYear :
2010
Firstpage :
1753
Lastpage :
1757
Abstract :
This paper presents a very low power/area design for the advanced encryption standard (AES) based on an 8-bit data path. The average measured core power on a 0.13-μm CMOS using a 100-kHz clock and a core voltage of 0.75 V is 692 nW. The core area is 21 000 μm2 and the latency is 356 cycles. This design further challenges the low-resource end of the design space and is the first reported submicrowatt design for the AES; it has significant power-latency-area performance improvements over the previous state-of-the-art application-specific IC (ASIC) implementations.
Keywords :
CMOS integrated circuits; application specific integrated circuits; cryptography; low-power electronics; ASIC; CMOS; advanced encryption standard; application-specific IC; average measured core power; core area; core voltage; frequency 100 kHz; power 692 nW; power-latency-area performance; size 0.13 mum; voltage 0.75 V; word length 8 bit; Application specific integrated circuits; Clocks; Cryptography; Delay; Energy consumption; Field programmable gate arrays; HDTV; IP networks; NIST; Throughput; Advanced encryption standard (AES); application-specific integrated circuit (ASIC); efficient design; low area; low power; low resource;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2009.2025952
Filename :
5256141
Link To Document :
