Theory of safe replacements for sequential circuits

We address the problem of developing suitable criteria for design replacement in the context of sequential logic synthesis. There have been previous efforts to characterize replacements for such designs. However, all previous attempts either make implicit or explicit assumptions about the design or the environment of the design. For example, it is widespread practice to assume the existence of a hardware reset line and, consequently, a fixed power-up state; in the absence of the same, a common premise is that the design´s environment will apply an initializing sequence. We present the notion of safe replaceability, which does away with these assumptions, and prove a number of properties that hold of it. Most importantly, we show that the notion is sound, i.e., if design D₁ is a safe replacement for design D₀ , then no environment can determine if D₁ is used in place of D₀ and that the notion is complete, i.e., if D₁ is not a safe replacement for D₀ then there exists an environment that can detect if D₁ is used in place of D₀ . Completeness is important for logic synthesis and verification because it specifies the maximum allowable flexibility for replacement. When the design´s output is not used for a certain number of cycles after power up, then safe replaceability can be relaxed to obtain what we refer to as delay safe replaceability; we analyze properties of this notion too. Since our work, many papers have used this notion effectively for sequential optimization