Hardware acceleration with pipelined adder for Support Vector Machine classifier

In this paper, a hardware implementation of Support Vector Machine (SVM) classifier for acceleration has been proposed based on pipelined adder, in which the speedups outperform other existing architectures. The adder whose critical path has been efficiently shortened by pipeline technology, constituted the main arithmetic elements in SVM processing. Therefore, a higher processing frequency and throughput have been achieved. Synthesize results in Design Compiler have shown that the operating frequency of the parallel processing elements can reach to 1.16GHz. 1.44X and 1.21X speedups are gained compared with implementations using RCA and KS adder with little area overhead and 3.5X GMACs improvement than other existing architectures on FPGA is obtained.