DocumentCode :
1447783
Title :
Floorplanning using a tree representation
Author :
Guo, Pei-Ning ; Takahashi, Toshihiko ; Cheng, Chung-Kuan ; Yoshimura, Takeshi
Author_Institution :
Mentor Graphics Corp., San Jose, CA, USA
Volume :
20
Issue :
2
fYear :
2001
fDate :
2/1/2001 12:00:00 AM
Firstpage :
281
Lastpage :
289
Abstract :
We present an ordered tree (O tree) structure to represent nonslicing floorplans. The O tree uses only n(2+[lg n]) bits for a floorplan of n rectangular blocks. We define an admissible placement as a compacted placement in both x and y directions. For each admissible placement, we can find an O-tree representation. We show that the number of possible O-tree combinations is O(n!22n-2/nl.5). This is very concise compared to a sequence pair representation that has O((n!)2) combinations. The approximate ratio of sequence pair and O-tree combinations is O(n2(n/4e)n). The complexity of O tree is even smaller than a binary tree structure for slicing floorplan that has O(n!25n-3/n1.5) combinations. Given an O tree, it takes only linear time to construct the placement and its constraint graph. We have developed a deterministic floorplanning algorithm utilizing the structure of O tree. Empirical results on MCNC (www.mcnc.org) benchmarks show promising performance with average 16% improvement in wire length and 1% less dead space over previous central processing unit (CPU) intensive cluster refinement method
Keywords :
circuit layout CAD; computational complexity; integrated circuit layout; redundancy; trees (mathematics); wiring; MCNC benchmarks; admissible placement; binary tree structure; compacted placement; constraint graph; dead space; deterministic floorplanning algorithm; intensive cluster refinement method; linear time; nonslicing floorplans; ordered tree structure; rectangular blocks; sequence pair representation; tree representation; wire length; Binary trees; Central Processing Unit; Circuits; Clustering algorithms; Graphics; National electric code; Process design; Tree graphs; Wire; World Wide Web;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.908471
Filename :
908471
Link To Document :
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