A bipartition-codec architecture to reduce power in pipelined circuits

Author

Ruan, Shanq-Jang ; Shang, Rung-Ji ; Lai, Feipei ; Tsai, Kun-Lin

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

20

Issue

2

fYear

2001

fDate

2/1/2001 12:00:00 AM

Firstpage

343

Lastpage

348

Abstract

This paper proposes a new approach to synthesize pipelined circuits with low-power consideration. We treat each output value of a combinational circuit as one state of a finite-state machine (FSM). If the output of a combinational circuit transits mainly among some few states, we could extract those states (output) and the corresponding input to build a subcircuit. After bipartitioning the circuit, we apply the encoding technique to the highly active subcircuit for further power reduction. In this paper, we formulate the bipartition problem and present a probabilistic-driven algorithm to bipartition a circuit so as to minimize the power dissipation. Our experimental results show that an average power reduction on several Microelectronic Center of North Carolina (MCNC) benchmarks of 31.6% is achievable

Keywords

Hamming codes; codecs; combinational circuits; finite state machines; logic partitioning; low-power electronics; pipeline processing; MCNC benchmarks; active subcircuit; average power reduction; bipartition-codec architecture; combinational circuit; finite-state machine; low-power consideration; output value; pipelined circuits; power reduction; probabilistic-driven algorithm; subcircuit; Circuit synthesis; Clocks; Combinational circuits; Computer science; Coupling circuits; Encoding; Input variables; Logic; Microelectronics; Power dissipation;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.908477

Filename

908477