DocumentCode :
1448153
Title :
Parametric fault identification and dynamic compensation techniques for cellular neural network hardware
Author :
Grimaila, M.R. ; De Gyvez, J. Pineda
Author_Institution :
Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
Volume :
143
Issue :
5
fYear :
1996
fDate :
10/1/1996 12:00:00 AM
Firstpage :
295
Lastpage :
301
Abstract :
Testing strategies to quantify parametric faults in a fully programmable, two-dimensional cellular neural network (CNN) are presented. The approach is intended to quantify system offsets, time constant mismatches, nonlinearities in the multipliers and state nodes, and the magnitude of the dynamic range of operation which can lead to misconvergence in the CNN array. For some cases, the authors present dynamic solutions by compensating the templates, the input data, and/or the initial condition values to minimise or cancel the undesired effects. The proposed dynamic compensation techniques can be applied to any CNN independent of the array size or topology. To demonstrate the feasibility of the proposed techniques, the authors examine their application to an actual complex VLSI CNN implementation
Keywords :
CMOS integrated circuits; VLSI; cellular neural nets; compensation; fault diagnosis; image processing equipment; integrated circuit testing; CCD; CMOS; cellular neural network hardware; complex VLSI CNN implementation; dynamic compensation; dynamic range; dynamic solutions; feasibility; misconvergence; nonlinearities; parametric fault identification; programmable 2D cellular neural network; system offsets; time constant mismatches;
fLanguage :
English
Journal_Title :
Circuits, Devices and Systems, IEE Proceedings -
Publisher :
iet
ISSN :
1350-2409
Type :
jour
DOI :
10.1049/ip-cds:19960478
Filename :
543701
Link To Document :
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