Title :
Low-power multirate architecture for IF digital frequency down converter
Author :
Jou, Shyh-Jye ; Wu, Shou-Yang ; Wang, Chorng-Kuang
Author_Institution :
Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
fDate :
11/1/1998 12:00:00 AM
Abstract :
In this paper, a novel low-power multirate architecture for an IF digital frequency downconversion process is presented. The architecture design is the combination of 4-IF oversampling technique and multistage interpolated finite impulse response (IFIR) filter design based on the multirate algorithm. It can have very low-power dissipation owing to its reduction in hardware complexity and operational frequency. The design example shows that it consumes only 24% of the power of the direct implementation while occupying 26% less area
Keywords :
CMOS digital integrated circuits; FIR filters; digital filters; digital radio; frequency convertors; interpolation; radio receivers; signal sampling; 4-IF oversampling technique; IF digital frequency down converter; finite impulse response filter; low-power dissipation; low-power multirate architecture; multirate algorithm; multistage interpolated FIR filter design; Algorithm design and analysis; Baseband; Digital-to-frequency converters; Finite impulse response filter; Frequency conversion; Hardware; Modulation; Power dissipation; Receivers; Sampling methods;
Journal_Title :
Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on