Title :
A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s Logarithmic Pipeline ADC
Author :
Lee, Jongwoo ; Kang, Joshua ; Park, Sunghyun ; Seo, Jae-sun ; Anders, Jens ; Guilherme, Jorge ; Flynn, Michael P.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Univ. of Michigan, Ann Arbor, MI, USA
Abstract :
A switched-capacitor logarithmic pipeline analog-to-digital converter (ADC) that does not require squaring or any other complex analog function is presented. This approach is attractive where a high dynamic range (DR), but not a high peak SNDR, is required. A prototype signed, 8-bit 1.5 bit-per-stage logarithmic pipeline ADC is designed and fabricated in 0.18 mum CMOS. The 22 MS/s ADC achieves a measured DR of 80 dB and a measured SNDR of 36 dB, occupies 0.56 mm2, and consumes 2.54 mW from a 1.62 V supply. The measured dynamic range figure of merit is 174 dB.
Keywords :
CMOS integrated circuits; analogue-digital conversion; capacitors; image processing; pipeline arithmetic; CMOS; analog-to-digital converter; dynamic range; power 2.5 mW; power 2.54 mW; size 0.18 mum; storage capacity 8 bit; switched-capacitor logarithmic pipeline ADC; voltage 1.62 V; Analog-digital conversion; Dynamic range; Encoding; Image coding; Pipelines; Prototypes; Quantization; Signal resolution; Switching converters; Voltage; Compander; logarithmic ADC; pipeline ADC;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.2009.2028052
